1. Field of the Invention
The present invention relates to Analog to Digital (A/D) converters for converting analog signals to a digital signals, and to a recorded data reproducing apparatus for reading out write data from a recording medium.
2. Description of the Related Art
Recently, A/D converters have been used in various electronic devices which have a growing demand for faster A/D conversion. A typical A/D converter comprises a plurality of comparator sections for comparing analog input signals with analog reference voltages and an encoder section for converting the output signals of the comparator sections to digital signals consisting of a plurality of bits. To increase A/D conversion speed, it is necessary to improve the operation speeds of both the comparator sections and the encoder sections.
One type of A/D converter is a parallel type A/D converter, which is superior to other types of A/D converters in terms of A/D conversion speed. FIG. 1 shows a conventional parallel type A/D converter, which outputs a 5-bit digital output signal. Thirty-two resistors R are connected in series between a high-potential reference voltage supply VRH and a low-potential reference voltage supply V.sub.RL. Each of the two resistors R respectively located at the top and bottom ends of the resistor series circuit has half the resistance of each of the other thirty resistors R.
The A/D converter includes thirty-one comparators CM1 to CM31 each having first and second input terminals. Thirty-one nodes between the thirty-two resistors R are connected to the first input terminals of the comparators CM1-CM31, respectively. Therefore, the individual comparators CM1-CM31 are respectively supplied with reference voltages V.sub.R1 to V.sub.R31, which are determined by dividing the potential difference between high and low reference voltages V.sub.RH and V.sub.RL by the resistors. An analog input signal A.sub.in is supplied to the second input terminals of the comparators CM1-CM31. The comparators CM1-CM31 operate based on a control signal output from a control circuit (not shown) and compare the analog input signal A.sub.in with the respective received reference voltage signal V.sub.R1 -V.sub.R31.
The comparators CM1-CM31 have an identical structure and the internal circuit of each comparator is illustrated in FIG. 2. The first and second input terminals receive a reference voltage V.sub.R and an analog input signal A.sub.in, respectively, and are connected to a node N13 which is the first terminal of a capacitor C3 via switch circuits SW11 and SW10, respectively. The switch circuits SW10 and SW11 are controlled by a pair of associated control signals CS4 and CS5 provided by the aforementioned control circuit, and are switched on when the associated control signals CS4 and CS5 are high.
A node N14 represents a second terminal of capacitor C3 which is connected to the input terminal of an inverter circuit 4h whose output terminal is connected to its input terminal via a switch circuit SW12. The switch circuit SW12 is controlled based on the control signal CS4, and is switched on when the control signal CS4 goes high. The output signal of the inverter circuit 4h is supplied via a capacitor C4 to an inverter circuit 4i whose input and output terminals are connected together via a switch circuit SW13. The switch circuit SW13 is controlled by the control signal CS5, and is switched on when the control signal CS5 goes high. An output signal S is output by the output terminal of the inverter circuit 4i and is also inverted by an inverter circuit 4j, yielding an output signal /S.
The operation of the comparator CM shown in FIG. 2 will be now described with reference to FIG. 3. When control signal CS5 is at a L (Low) level and control signal CS4 is at a H (High) level, the switch circuit SW11 is switched off and the switch circuits SW10, SW12 and SW13 are switched on. As a result, the potentials at node N14 and the output terminal of the inverter circuit 4h are reset to a threshold voltage of the inverter circuit 4h. This causes the charge current to flow into the capacitor C3 and causes the potential at node N13 to become the potential level of the analog input signal A.sub.in. The potentials at the input and output terminals of the inverter circuit 4i are reset to a threshold voltage of the inverter circuit 4i.
When the control signal CS4 goes low and the control signal CS5 goes high, the switch circuits SW10, SW12 and SW13 are switched off and the switch circuit SW11 is switched on. Consequently, the reference voltage V.sub.R is compared with the potential level of the analog input signal A.sub.in. When the reference voltage V.sub.R is higher than the potential level of the analog input signal A.sub.in, the potential at node N14 becomes higher than the threshold voltage of the inverter circuit 4h due to capacitive coupling by the capacitor C3, and the output signal of the inverter circuit 4h becomes low. As a result, the potential level on the input side of the inverter circuit 4i becomes lower than the threshold voltage of this inverter circuit 4i due to capacitive coupling by the capacitor C4. Consequently, the output signal S goes high and the output signal /S goes low.
When the reference voltage V.sub.R is lower than the potential level of the analog input signal A.sub.in, the potential at node N14 becomes lower than the threshold voltage of the inverter circuit 4h due to capacitive coupling by the capacitor C3, and the output signal of the inverter circuit 4h goes high. As a result, the potential level on the input side of the inverter circuit 4i becomes higher than the threshold voltage of this inverter circuit 4i due to capacitive coupling by the capacitor C4. Consequently, the output signal S goes low and the output signal /S goes high.
When the control signal CS4 goes high and the control signal CS5 goes low, the potential at node N13 is reset to the potential level of the analog input signal A.sub.in and the potentials at the input and output terminals of the inverter circuits 4h and 4i are reset to the threshold voltages of the associated inverter circuits 4h and 4i. When the levels of the control signals CS4 and CS5 are changed, the reference voltage V.sub.R is (once again) compared with the potential level of the analog input signal A.sub.in and the above-described operation will be repeated.
When the potential level of the analog input signal A.sub.in is lower than the received reference voltage (one of V.sub.R1 to V.sub.R31), each of the comparators CM1 to CM31 (each having the internal structure shown in FIG. 2) outputs an H (High)-level output signal (one of output signals S1 to S31) and an L (Low)-level output signal (one of signals /S1 to /S31). On the other hand, when the potential level of the analog input signal A.sub.in is higher than the received reference voltage (voltages V.sub.R1 to V.sub.R31), each comparator outputs an L-level output signal (one of the signals S1 to S31) and an H-level output signal (one of the signals /S1 to /S31).
For example, when the potential level of analog input signal A.sub.in is higher than a reference voltage V.sub.R4 but lower than the reference voltage V.sub.R1, output signals S1 to S4 corresponding to comparators CM1 to CM4 will go high, while output signals /S1 to /S4 will go low. Output signals S5 to S31 representing the upper twenty-seven comparators CM5 to CM31 will go low while output signals /S5 to /S31 go high.
The output signals S1-S31 and /S1-/S31 of the comparators CM1-CM31 are coupled to thirty-two 2-input NOR gates DE0 to DE31, which function as an address decoder. More specifically, the output signals S1-S31 of the comparators CM1-CM31 are supplied to the first input terminals of the NOR gates DE1 to DE31, while the output signals /S1-/S31 of the comparators CM1-CM31 are supplied to the second input terminals of the NOR gates DE0 to DE30. Each of the NOR gates DE0 and DE31 have one input terminal connected to ground GND.
With this structure, when both input signals become L-level, each of the NOR gates DE0-DE31 output a H-level signal. When comparators CM1-CM31 are patterned this way, only one of the thirty-two NOR gates outputs an H-level signal.
The output signals of the NOR gates DE0-DE31 are supplied to thirty-two word lines WLO to WL31 of an encoder 1 which represents a ROM. The encoder 1 has five bit lines BL0 to BL4 laid out in association with 1-bit digital output signals D0 to D4 consisting of a total of five bits. A plurality of ROM cells 2 are connected between the word lines WL0-WL31 and the bit lines BL0-BL4 so as to be able to produce 2.sup.5 (=32) binary signals. Each ROM cell 2 has an N channel MOS transistor which has a gate connected to the associated word line, a drain connected to the associated bit line and a source connected to the ground GND, as shown in FIG. 4.
As shown in FIG. 1, the bit lines BL0-BL4 are connected to a power supply V.sub.DD via switch circuits SW0 to SW4, respectively. When switch circuits SW0-SW4 are switched on, the bit lines BL0-BL4 are precharged. Each of the switch circuits SW0-SW4 is consists of a P channel MOS transistor.
When the potential level of one of the word lines goes high after the switch circuits SW0-SW4 are opened, the ROM cells 2 connected to that word line are enabled and the potential levels of the bit lines which are connected to those ROM cells 2 goes low. For example, when potential level of the word line WL0 goes high, the digital output signals D0-D4 consisting of a total of five bits become "00000". When potential level of the word line WL2 goes high, the digital output signals D0-D4 become "00010".
FIG. 5 illustrates another conventional parallel A/D converter for a 2-bit digital output. Four resistors R are connected in series between a high-potential reference voltage supply V.sub.RH and a low-potential reference voltage supply V.sub.RL. Each of the two resistors R respectively located at the top and bottom ends of the resistor series circuit have half the resistance of each of the two remaining resistors R. The A/D converter further includes an encoder section 3, a control circuit 4 and three comparators CM1 to CM3 each having first and second input terminals.
Three nodes between the individual resistors R are respectively connected to the first input terminals of the comparators CM1-CM3. Therefore, each of the individual comparators CM1-CM3 is respectively supplied with reference voltages V.sub.R1 to V.sub.R3. An analog input signal A.sub.in is supplied to the second input terminals of the comparators CM1-CM3.
As a result, the individual comparators CM1-CM3 compare the analog input signal A.sub.in with each of the received reference voltage signal V.sub.R1 to V.sub.R3. When the potential level of the analog input signal A.sub.in is higher than the received reference voltage signals, the comparators CM1-CM3 output H-level output signals S1-S3. On the other hand, when the potential level of the analog input signal A.sub.in is lower than the received reference voltage signals, the comparators CM1-CM3 output L-level output signals S1-S3. For example, when the potential level of the analog input signal A.sub.in is higher than the reference voltage V.sub.R2 but lower than the reference voltage V.sub.R3, output signals SG1 and SG2 go high and an output signal SG3 goes low. That is, the output signals SG1 to SG3 behave according to a thermometer code. In accordance with the thermometer code, the output signal of the comparator which is supplied with the reference voltage lower than the potential level of the analog input signal A.sub.in goes to an H-level, while the output signal of the comparator which is supplied with a reference voltage higher than the potential level of the analog input signal A.sub.in goes to an L-level.
The output signals SG1-SG3 are supplied to the encoder section 3 from the comparators CM1-CM3. The operation timings of the comparators CM1-CM3 and the encoder section 3 are controlled by the control circuit 4. The address decoder and the encoder section 3 output digital output signals D0 and D1, each consisting of a single bit.
Referring now to FIG. 6. The comparators CM1-CM3 are shown being a chopper type. The two input terminals of each comparator, which respectively receive a reference voltage V.sub.R and an analog input signal A.sub.in, are connected via associated switch circuits SW5 and SW6 to a node N11 at the input-side end of a capacitor C1. The switch circuits SW5 and SW6 are controlled by a control signal CS1 and a control signal CS2 from the control circuit 4 of FIG. 5. In other words, the switch circuits SW5 and SW6 are switched on when control signals CS1 and CS2 go high.
A node N12 at the second end of capacitor C1 is connected to the input terminal of an inverter circuit 4a, and is also connected to the output terminal of the inverter circuit 4a via a switch circuit SW7. Switch circuit SW7 is controlled by the control signal CS1 such that it is switched on when the control signal CS1 goes high. The output signal of the inverter circuit 4a is supplied to the input terminal of an inverter circuit 4c via an inverter circuit 4b and a switch circuit SW8. This switch circuit SW8 is controlled by a control signal CS3 so that it is switched on when the control signal CS3 goes high.
The output signal of the inverter circuit 4c is inverted by an inverter circuit 4e and the inverted signal is sent out as an output signal OUT. Further, the output signal of the inverter circuit 4c is returned to the inverter circuit 4c via an inverter circuit 4d and a switch circuit SW9. This switch circuit SW9 is controlled by a control signal /CS3, representing an inverted control signal CS3, such that it is switched on when the control signal /CS3 goes high.
The operation of the chopper type comparator shown in FIG. 6 will now be discussed with reference to FIG. 7. Control signals CS2 and CS3 are supplied as inverted signals of control signal CS1. When the control signal CS1 goes high and the CS2 goes low, the switch circuits SW5 and SW7 are switched on and the switch circuit SW6 is switched off. Consequently, the potential at node N12 is reset to the threshold voltage of the inverter circuit 4a, allowing the charge current to flow into the capacitor C1 so that the potential level at node N11 becomes the level of the reference voltage V.sub.R.
When control signal CS1 goes low and control signals CS2 and CS3 go high then, the switch circuits SW5 and SW7 are switched off and the switch circuit SW6 is switched on. Consequently, the reference voltage V.sub.R is compared with the potential level of analog input signal A.sub.in. When the potential level of the analog input signal A.sub.in is higher than the reference voltage V.sub.R, the potential at node N12 becomes higher than the threshold voltage of the inverter circuit 4a due to capacitive coupling by the capacitor C1. When the potential level of the analog input signal A.sub.in is lower than the reference voltage V.sub.R, the potential at node N12 becomes lower than the threshold voltage of the inverter circuit 4a of FIG. 6. As the switch circuit SW8 is switched on at this time, the output signal of the inverter circuit 4a is supplied to the inverter circuit 4c via the inverter circuit 4b and the switch circuit SW8. The output signal of the inverter circuit 4c is sent out as an output signal OUT via the inverter circuit 4e.
When the control signal CS1 goes high and the control signals CS2 and CS3 go low again, the potential at node N11 is reset to the potential level of the reference voltage V.sub.R and the potential level at node N12 is reset to the threshold voltage of the inverter circuit 4a. In this case, switch circuit SW9 is switched on. As a result, the inverter circuits 4c and 4d constitute a latch circuit that latches the output signal OUT. When the levels of the control signals CS1 to CS3 are changed, the potential level of the analog input signal A.sub.in is compared again with the reference voltage V.sub.R and the above-described operation will be repeated.
In the conventional analog to digital (A/D) converter shown in FIG. 1, sixteen N channel MOS transistors are connected as the ROM cells 2 to the five bit lines BL0 to BL4 in the encoder 1. The number of the necessary transistors doubles as the number of the digital output signal increases by one bit. Unfortunately, increasing the number of bits of a digital output signal generally tends to increase the parasitic capacitance of each bit line. This increases the load with respect to each ROM cell 2, which also decreases the operation speed of the encoder 1 and increases power consumption during the precharge operation.
When the potential difference between two reference voltages V.sub.Rn and V.sub.Rn+1 decreases due to an increased number of bits of the output signal, or when noise is mixed in with the reference voltages V.sub.RH and V.sub.RL or the analog input signal A.sub.in, the output signals between a plurality of adjacent sets of comparators may be inverted. In such a case, unfortunately, two or more NOR gates output H-level output signals simultaneously so that an erroneous digital output signal is produced.
One proposed way to prevent this erroneous operation is to provide the address decoder with an error correcting function. This proposal, however, complicates the circuit design of the address decoder.
The output signals S of the chopper type comparators CM1-CM31 should have amplitudes high enough for the NOR gates DE0-DE31 at a subsequent stage to identify whether the associated output signals S are "0" or "1". At the time of the comparison, however, the output signals S from the chopper type comparators CM1-CM31 have full amplitudes which vary between the high potential level of the high-potential reference voltage supply and the low potential level of the low-potential reference voltage supply. It therefore takes time for the reset operation of resetting the potential levels at the input and output terminals of the inverter circuits 4h and 4i to the threshold voltages thereof from the potential level of the high-potential reference voltage supply or the potential level of the low-potential reference voltage supply.
Therefore, even if the frequencies of control signals CS4 and CS5 are increased to improve the operation speed, the reset operation and the comparison operation cannot follow up the changes in control signals CS4 and CS5. It is apparent from this situation that when the speed of the reset operation is slower than the operation speed of the encoder 1, the speed of analog to digital conversion is limited by the speed of the reset operation, as such the speed of the A/D conversion cannot be increased.
Likewise, the comparators CM1-CM3 of the A/D converter shown in FIG. 5 repeat the operation of resetting the potentials at nodes N11 and N12 and the comparison of the reference voltage V.sub.R with the analog input signal A.sub.in. In other words, half of the A/D conversion time is spent during the reset operation. This is one cause of making the A/D conversion slower. Even if the frequencies of the control signals CS1-CS3 are increased in an attempt to improve operation speed, the reset operation and the comparison operation through the capacitor C1 cannot follow up the changes in the control signals CS1-CS3. Thus, the speed of the A/D conversion cannot be increased.
If the number of comparators is increased to increase the number of bits of a digital output signal, charge and discharge currents simultaneously flow between the source of the reference voltage V.sub.R and the capacitor C1 of each comparator in the reset operation, and charge and discharge currents simultaneously flow between the source of the analog input signal A.sub.in and each capacitor C1 in the comparison operation. Because the input and output terminals of the inverter circuits 4a of the individual comparators are reset to the threshold voltages at a time, a flowthrough current simultaneously flows into the individual inverter circuits 4a. Noise is therefore apt to be produced in the reference voltage V.sub.R, the analog input signal A.sub.in and the supply voltages so that an erroneous operation is likely to occur due to the noise.
This patent application will also discuss a recorded data reproducing apparatus for reading out written data from a recording medium like a magnetic disk.
Data which is read from a magnetic hard disk by a reading head is supplied as an analog signal. The analog signal of the read data is converted to a digital signal by an A/D converter. This digital signal undergoes various kinds of digital processes to be reproduced as recorded data. To increase the speed of such reproduction of recorded data, recently, attempts have been made to improve the data recording density of a recording medium and improve the speed of processing digital signals. There is thus a need to improve the precision of A/D converters that are used in recorded data reproducing apparatuses.
In a typical recorded data reproducing apparatus, analog data read from a recording medium like a magnetic disk by the reading head is amplified by an amplifier and the output signal of that amplifier is supplied to an A/D converter via an analog equalizer filter. The A/D converter converts the input analog signal to a digital signal and supplies the digital signal to a digital processing circuit located at the next stage. The digital processing circuit performs digital processing such as a decoding process on the received digital signal to reproduce recorded data.
An offset voltage may occur in the signal that is input to the A/D converter via the analog equalizer filter due to a change in ambient temperature, a variation in power supply voltage or a chronological change in the precision of individual circuits located at the preceding stage of the magnetic disk and the A/D converter. When an offset voltage is produced in the input signal to the A/D converter, the accurate A/D conversion becomes impossible. It is known to provide an offset canceling circuit for canceling an offset voltage is provided on the input side of the A/D converter.
The offset canceling circuit includes a circuit for canceling an offset voltage based on the adjustment of an external part like a resistor, or a feedback circuit which provides an external MPU with the output signal of the A/D converter, converts a digital control signal computed by the MPU based on the output signal of the A/D converter to an analog signal by a D/A converter and uses the analog signal to cancel an offset voltage.
However, the offset canceling circuit using an external part cannot properly cope with a variation in offset voltage. Hence, the use of such offset canceling circuits cannot sufficiently improve the precision of A/D conversion.
The use of the offset canceling circuit which cooperates with an external MPU cannot be a decisive factor to accomplish an A/D conversion with an excellent precision for at least the following reason. If the A/D conversion speed of an A/D converter is increased in accordance with recent improvements in the speed at which data can be read, the amount of the computation of the digital control signal by the MPU increases. This increases the load on the MPU, which brings about new problems such as delaying other processes that should be executed by the MPU.